Write a short mote a interconnect.

Write a short mote a interconnect.

Ans. The most important additions for CMOS logic processes are additional signal-and power-routing layers which are known as interconnect. This eases the routing of logic signals between modules and improves the power and clock distribution to modules. Improved routability is obtained through additional layers of metal or by improving the existing poly silicon interconnection layer.

(i) Metal Interconnect – The second level of metal is almost mandatory for modern CMOS digital design. A third layer is becoming common and is certainly needed for leading-edge high-density, high-speed chips. Generally, aluminum is used for the metal layers. When some form of planarization is used, the second-level metal pitch can be the same as the first. As the vertical topology becomes more varied, the width and spacing of metal conductors has to increase so that the conductors do not thin and hence break at vertical topology jumps (step coverage).

As shown in fig. 5.10, contracting the second-layer metal to the first-layer metal is obtained by a via. When further contact to diffusion or poly silicon is needed, a separation between the via and the contact cut is usually needed. This needs a first-level metal tub to bridge between metal2 and the lower-level conductor. In contemporary processes, first-level metal must be involved in any contact to underlying areas. Processes usually need metal borders around the via on both levels of metal although some processes need none.

5.10

For a two metal process, the process steps are briefly as follows –

  • Oxide below the first-metal layer is deposited by atmospheric chemical vapour deposition (CVD).
  • Second oxide layer between the two metal layers is applied in a similar fashion.
  • Depending on the process, removal of the oxide is carried out using a plasma etcher designed to have a high rate of vertical ion bombardment, which permits fast and uniform etch rates. The structure of a via etched using such a method is shown in fig. 5.10.

(ii) Poly silicon/Refractory Metal Interconnect – Generally, the poly silicon layer used for the gates of transistors is used as an interconnect layer. But, the sheet resistance of doped poly silicon is between 20 and 40 /square. When used as a long distance conductor, a poly silicon wire can denote a significant delay.

One method to improve this is to decrease the poly silicon resistance by combining it with a refractory metal. This method requires no extra mask levels. There such approaches are deoicted in fig. 5.11. in fig. 5.11(a), a silicide (e.s., silicon and tantalum) is used as the gate material. Sheet resistances of the order of 1 to 5 /square may be obtained. This is known as the silicide gate approach. Silicides are mechanically strong and may be dry etched in plasma reactors. Tantalum silicide is stable throughout standard processing and has the benefit that it can retro fitted into existing process lines. In fig. 5.11(b), a sandwich of silicon upon poly silicon is used which is commonly known as the poly cide approach. Lastly, the silicide/poly silicon approach may be extended to include the formation of source and drain regions using the silicide. This is known as the Salicide process (Self Aligned SILICIDE) fig. 5.11(c). The effect of all of these processes is to reduce the “second later” interconnect resistance, permitting the gate material to be used as a moderate long-distance interconnect. This is obtained by minimum perturbation of an existing process.

5.11

(iii) Local Interconnect – Silicon itself can be employed s a “local interconnect” layer for connection within cells. For instance, TiN is used. Local interconnect permits a direct connection between poly silicon and diffusion, hence alleviating the requirement for area-intensive contacts and metal. Fig. 12 depicts a portion (p-devices only) of a six transistor SRAM cell which uses local interconnect. The local interconnect has been used to make the poly silicon-to-diffusion connection within the cell, thereby alleviating the requirement to use (and contacts). Metal 2 bit lines run over the cell vertically. Use of local connect in this RAM reduced the cell area by 25%. Normally, local interconnect if available can be used to complete intra cell routing leaving the remaining metal layers for global wiring.

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