What do you understand by internal latch up prevention techniques.

What do you understand by internal latch up prevention techniques.

Ans. According to fig. 5.17(B), we observe that the emitter of the npn-transistor has to an NMOS transistor source returned to VSS. The well resistor takes place between the p+ source nominally to VDD and the n+ well contact. The substrate resistor takes place between the emitter and the supply shown by a substrate resistor contact. Clearly, if the n-transistor source is shorted to the p+ substrate contact, much has been done to decrease Rsubstrate. Thus a key technique to decrease latch up is to make good use of substrate and well contacts.

In most current processes the possibility of latch up occurring in internal circuitry has been decreased to the point where a designer need not worry about the effect as long as liberal substrate contacts are used.

The definition of “liberal” is usually acquired from designers who have completed successful designs through a given process. Modeling the parasitic is possible, but the actual switching transients existent in the circuit have a great effect on any possible latch up condition. A few rules may be followed that decrease the possibility of internal latch up to a very small probability –

  1. Every substrate contact should be connected to metal directly to a supply pad i.e., no diffusion or poly silicon underpasses in the supply rails.
  2. Every well must have a substrate contact of the appropriate type.
  3. Place substrate contacts as close as possible to the source connection of transistors connected to the supply rails. This decreases the value of Rsubstrate and Rwell. A very conservative rule would place one substrate contact for every supply VSS or VDD
  4. Otherwise a less conservative rule is place a substrate contact for every 5=10 transistors or every 25-100.
  5. Layout p-and n-transistors with packing of p-devices toward VDD and packing of n-devices toward VSS.


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