Explain the twin-tub process for CMOS fabrication.

Explain the twin-tub process for CMOS fabrication.

Ans.  Twin-tup fabrication process is a logical extension of the p-well and n-well approaches. In this process, we with a substrate of high resistivity p-type material and then create both n-well regions. It is possible to preserve the performance of n-transistors without compromising the p-transistors through this process. Doping control is more readily obtained and some relaxation manufacturing tolerances results. This is particularly important as far as latch-up is concerned. Generally, the twin-tub process permits separate optimization of the n-and p- transistors.

Fir. 5.9 shows the important steps in a twin-tub process. Details can vary from process to process, but these steps are representative. First step is to put tubs into the wafer at the proper places for the n-type and p-type wafers. The regions on the wafer are selectively doped by implanting ionized do pant atoms into the material, then heating the wafer to heal damage caused by ion implantation and further move the do pants by diffusion. Tub structure means that n-type and p-type wires cannot directly connect. Because the two diffusion wire types must exist in different type tubs, there is no way to form a via that can directly connect them. Connections must be established by a separate wire, generally metal, that runs over the tubs.

5.9

Next steps build an oxide covering of the wafer and the poly silicon wires. The oxide is built in two steps – first, a thick field oxide is grown over the entire wafer. Field oxide is etched away in areas directly over transistors; a separate step grows a much thinner oxide that will make the insulator of the transistor gates. After the field and thin oxides have been grown, poly silicon wires are made by depositing poly silicon crystalline directly on the oxide.

It should be noted that the poly silicon wires have been laid down before the diffusion wires were formed – that order is critical to the success of MOS processing. Diffusion wires are laid down just after poly silicon deposition to generate self-aligned transistors – the poly silicon masks the formation of diffusion wires in the transistor channel. There must be no gap between the ends of the source and drain diffusion regions and the start of the transistor gate to work the transistor properly. If the diffusion were laid down first with a hole left for the poly silicon wire unless the transistor were made too large. Self-aligned processing permits much smaller transistors to be made.

To insulate the poly silicon and metal wires, another layer of oxide is deposited after the diffusion are complete. Aluminum has long been the dominant interconnect material, but copper has now moved into mass production. Copper is a much better conductor as compared to aluminum, but even trace amounts of it will destroy the properties of semiconductors. Chips with copper interconnect include a special protection layer between the substrate and the first layer of copper. That layer prevents the copper from entering the substrate in the processing duration.

Holes are cut in the field oxide where vias to the substrate are wanted. Then, metal 1 is deposited where desired. Metal fills the cuts to make connections between layers. Metal 2layer needs an additional oxidation/cut/deposition sequence. After all the important circuit features have been made, the chip is covered with a final passivation layer of SiO2 to protect the chip from chemical contamination.

 

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