Explain the physical structure and operation of an NMOS enhancement transistorRipunjay Tiwari
Ans. Fig. 1.8 shows the physical structure of an NMOS enhancement transistor, which consists of a moderately doped p-type silicon substrate into which two heavily dopen n+ regions, the source and drain, are diffused. A narrow region of p-type substrate exists between these two region, which is no as channel. This channel is covered by a thin insulating layer of silicon dioxide (SiO2) called gate oxide. There is a polycrystalline silicon electrode over this oxide layer which is referred to as gate.
The D.C. current from the gate to channel is essentially zero, because the oxide layer is an insulator. There is no physical distinction between the drain and source regions due to the inherent symmetry of the structure. The application of high gate fields is possible because SiO2 has relatively low loss and high dielectric strength.
In operation, a positive gate voltage is given between the source and the drain (Vds). When gate bias is zero (i.e., Vgs = 0), current does not flow from source to drain since they are effectively insulated from each other by the two reversed biased pn-junctions illustrated in fig. 1.8. But, when a voltage, which is positive with respect to the source and the substrate, is applied to the gate then it generates an electric field E across the substrate which attracts electrons toward the gate and repels holes. In case when gate voltage is sufficiently large, the region under the gate alters from p-type to n-type and gives a conduction path between the source and the drain. Under such a condition the surface of the underlying p-type silicon is called inverted.
Fig. 1.9 shows the initial distribution of mobile positive holes in a p-type silicon substrate of an MOS structure for a voltage, Vgs, much less than a voltage, Vt, that is the threshold voltage, This mode is referred to as accumulation mode. When Vgs becomes greater than Vt, the holes are repelled causing a depletion region under the gate. This is termed as depletion mode as shown in fig. 1.9. (b). if Vgs is further increased above Vt, this results in electrons being attracted to the region of the substrate under the gate. A conductive layer of electrons gives rise to the name inversion mode in the p-substrate, as shown in fig. 1.9.(c).
An MOS device acts like a voltage-controlled switch which conducts initially if the gate-to-source voltage, Vgs is equal to the threshold voltage, Vt. If a voltage Vgs is given between source and drain, with Vgs = Vt, the horizontal and vertical components of the electrical field because of the source-drain voltage and gate-to-substrate voltage interact, leading conduction to take place along the channel. Sweeping of the electrons in the channel from the source onward the drain is the responsibility of the electrons in the channel from the electric field associated with the drain-to-source voltage (that is, Vds >0).
When voltage from drain to source is raised, the resistive drop along the channel starts to change the shape of the channel characteristic. This is shown in fig. 1.10. the full gate voltage is effective in inverting the channel at the source end of the channel. But, at the drain end of the channel, only the difference between the gate and drain voltages is effective.
If the effective gate voltage (Vgs – Vt) is larger as compared to the drain voltage, then channel becomes deeper as Vgs is increased. This is referred to as the linear, resistive, nonsaturated or unsaturated region, in which the channel current Ids is a function of both gate and drain voltages. When Vds is greater than effective gate voltage, Vgd < Vt, and the channel becomes pinched-off, i.e., channel no longer reaches the drain. This is shown in fig. 1.10(c).