Explain briefly the latch up triggering and latch up prevention.

Explain briefly the latch up triggering and latch up prevention.

Ans.  Latch up Triggering – The parasitic npn-pnp circuit has to be triggered and the holding state has to be maintained for latch up to take place. Latch up can be triggered by transient currents or voltages which can take place internally to a chip during power-up or externally because of voltages or currents beyond normal operating ranges. Radiation pulses can also cause latch up. Two distinct methods are used for triggering – lateral triggering and vertical triggering.

  • Lateral triggering takes place when a current flows in the emitter of the lateral npn-transistor. The static trigger point is set as –

M

Where,

Vpnp-on~0.7 V – the turn-on voltage of the vertical pnp-transistor

Mnpn = common base gain of the lateral npn-transistor

Rwell = well resistance.

  • Vertical triggering takes place when a sufficient current is injected into the emitter of the vertical-pnp transistor. Similar to the lateral case, this current is multiplied by the common-base-current gain, that generates a voltage drop across the emitter base junction of the npn transistor because of the resistance, Rsubstrate. If the holding or sustaining point is entered, it represents a stable operating point provided the current needed to stay in the state can be maintained.

5.18a

5.18b

Current has to be injected into either the npn- or pnp-emitter to initiate latch up. During normal circuit this can take place because of supply voltage transients, but this is unlikely. But, these conditions can take place at the I/O circuits employed on a CMOS chip, where the internal circuit voltages meet the external world and large currents can flow. Hence, extra precautions require to be taken with peripheral CMOS circuits. Fig. 5.18(a) shows an example where the source of an NMOS output transistor experiences undershoot with respect to VSS because of some external circuitry. If the output dips below VSS by more than 0.7V, then the drain of the complementary case is shown in fig. 5.18(b) where the PMOS output transistor experiences an overshoot more than 0.7V beyond VDD. Whether or not in these cases latch up takes place depends on the pulse widths and speed of the parasitic transistors.

Latch up Prevention – For latch up to take place an analysis finds the following inequality has to be true –

M

M

This equation is the key to minimizing latch up to the point where it should never take place under normal circuit conditions. Hence, reducing the resistor values and reducing the gain of the parasitic transistors are the basis for eliminating latch up.

There are two basic ways to prevent the latch up –

  • Latch up resistance CMOS processes
  • Layout techniques.

 

A widely process option which decreases the gain of the parasitic transistors is the use of silicon staring-material with a thin epitaxial layer on top of a highly doped substrate, which reduces the value of the substrate resistor and also provides a sink for collector current of the vertical pnp-transistor. As the epi-layer is thinned, the latch up performance improves until a point where the up-diffusion of the substrate and the down-diffusion of any diffusion in subsequent high-temperature procession steps thwart needed device doping profiles. The so-called retrograde well structure is also used, which has a highly doped area at the bottom of the well, whereas the top of the well is more lightly doped. This preserves good characteristic for the PMOS transistors but decreases the well resistance deep in the well. A technique linked to these two approaches is to increases the holding voltage above the VDD supply.

To reduce the betas of the bipolar transistors to satisfy the condition set above is difficult. Nominally, for a 1  n-well process, the vertical pnp has a beta of 10-100, depending on the technology. The lateral npn-current-gain, which is a function of n+ drain to n-well spacing, is between 1 and 5.

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