Discuss the high-frequency MOSFET model in detail.Ripunjay Tiwari
Ans. The high0frequency MOSFET model can be obtained from the D.C. model by adding the identifiable parasitic capacitances to the D.C. model. Parasitic device capacitorts are voltage independent can be modeled as –
Where A denotes the area of the intersection of the two plates, demotes the dielectric constant and denotes the dielectric thickness. The voltage independent capacitors can be made up of those that the are operation-region dependent and those that are not.
The operation-region independent capacitors can be made up of those overlap capacitors that appear on the periphery of the MOSFET. Fig. 3.3 shows a top view of these parasitic capacitors.
The effective area of the overlap components of the gate – source capacitance is W.LD where W denotes the channel width and LD denotes the lateral diffusion of the source. From equation (i) the gate-source overlap capacitor CGSOL is obtained as
or CGSOL = CGSOW ……..(iii)
where Cgso = LD/t indicates the overlap capacitance per unit width of the gate and acts as an input parameter in SPICE to model the overlap capacitance. This parasitic capacitance has an area capacitance density of Cox as the dielectric thickness is the identical as the gate oxide thickness. If the parameter CGSOL is not entered in SPICE, then
CGSOL = W.(LD) (COX) ……..(iv)
The gate-bulk overlap capacitance CGBOL is linearly proportional to L and dependent upon d1 and d2 as shown in fig. 3.3. although, the dielectric thickness in not constant for this parasitic. The dielectric thickness of the gate-bulk overlap is essentially equal to the field oxide height on the sides farthest from the channel and equal to the thickness of the gate oxide on the sides adjacent on the channel. Since CGBOL is proportional to L, which is defined as
CGBOL = CGBOL ……..(v)
Where CGBO shows the total gate-bulk capacitance per unit length of the device and acts as an input parameter in SPICE to characterize the gate-bulk overlap. Since d1 and d2 are layout dependent and since thickness of field oxide is not taken into account in the MOSFET model, the parameter CGBO must be entered if the effects of gate-bulk overlap are to be comprised in the model. Practically, d1 = d2 = d where d denotes the minimum overlap of the poly over the moat. With this assumption, any bulk-substrate capacitance associated with a larger gate polysilicon region is accounted for by adding an additional parasitic capacitance to the circuit representation from gate to substrate.
Those capacitors that are voltage dependent are the pn junction capacitors. They take place between bulk and drain, bulk and source, and bulk and channel.
They can be modeled as –
Where, Cjo = Zero-bias junction capacitance density
A = Junction cross-sectional area
V = Forward bias voltage on the junction
N = Constant that characterizes the junction type
FC = Forward bias capacitance coefficient.
A cross-section view of a pn diffused junction is shown in fig. 3.4. The total junction capacitance associated with the reverse biased junction (for VF < FC. B) of either the source or drain can be defined as
Where, cJ = Zero-bias bottom capacitance area density
A = Junction bottom area
MJ = Bottom junction grading coefficient
CJSW = Zero-bias sidewall capacitance per unit length of the perimeter
P = Junction sidewall perimeter
MJSW = Sidewall grading coefficient.
If not input, CJ can be determined internally from Nsub, under the assumption of a step graded junction as –