## Discuss about the circuit elements.

Ans. Some common circuit element are discussed below –

(i) Resistor – In unaugmented processes, resistor can be built from any layer, with the final resistance depending on the resistivity of the layer. Building large resistances in a small area requires layers with high resistivity, particularly poly silicon and diffusion. Diffusion has a large capacitance to ground, making it unsuitable for high-frequency applications. Poly silicon gates are usually silicided to have low resistivity. The fix for this is to allow for undoped high-resistivity poly silicon. This is specified with a mask that blocks the silicon where high-value poly resistors are required. The resistivity can be tuned to around 300-1000s/square, depending on doping levels. Another material used for high quality resistors is nichrome, although this requires a special processing step.

A typical resistor layout is shown in fig. 5.13. This geometry is sometimes called a meander structure. A number of unit resistors have been used so that a variety of matched resistor value can be constructed. For instance, if 20 k, 10 k and 15 k ohm resistor were required, a unit value of 5 k could be used. Then three resistors (as shown) would construct a 15 k ohm resistor. The two resistors at the ends are called dummy register or fingers. They perform no circuit function, but replicate the proximity effects (such as etch and implant) that the interior resistors see during processing. This helps ensure that all resistors are matched.

Like integrated capacitors, the various resistor options have temperature and voltage coefficients. Foundry design manuals normally include these values.

(ii) Inductor – The desire to integrate inductors on chips has increased radically with the upsurge in interest in RF circuits. The most common monolithic inductor is the spiral inductor, which is a spiral of upper-level metal. A typical inductor is shown in fig. 5.14. As the process is planar, an underpass connection has to be made to complete the inductor. A typical equivalent model is also shown in fig. 14. In addition to the required L, there are several parasitic components. R_{s} is the series resistance of the metal (and contacts) used to form the inductor. C_{p} is the parallel capacitance to ground due to the area of the metal wires forming the inductor. C_{s} is the shunt capacitance of the underpass. Finally, R_{o} is an element that models the loss incurred in the resistive substrate.

Usually, when considering an inductor, the parameters of interest to a designer are its inductance, the Q of the inductor, and the self resonant frequency. High Q’s are sought to create low phase-noise oscillators, narrow filters, and low-loss circuits in general. Q_{values} for typical planar inductors on a bulk process are in the range from 5 to 10.

The number of turns n required to achieve some inductance L if the wire pitch is P = W + S is

where _{0} = 1.2 x 10^{-6} H/m is the permeability of free space. Higher quality inductors can also be manufactured using bond wires between I/O pads. The inductance of a wire of length I and radius is approximately

(iii) Capacitor – In a conventional CMOS process, capacitor can be constructed using the gate and source/drain of an MOS transistor, a diffusion area (to ground or V_{DD}), or a parallel metal place capacitor (using stacked metal layers). The MOS capacitor has good capacitance per area but is relatively non-linear if operated has voltage ranges. The diffusion capacitor cannot be used for a floating (but is useful as a bypass capacitor). The metal parallel plate capacitor has low capacitance per area. Normally the aim in suing a floating capacitor is to have the highest ratio of desired capacitance value to stray capacitance (to ground normally). The bottom metal plate contributes stray capacitance to ground.