Describe the CMOS latch up.

Describe the CMOS latch up.

Ans. If every silver lining has cloud, then the cloud that has plagued CMOS is a parasitic circuit effect known as “latch up”. This effect results in the shorting of the VDD and VSS lines, usually resulting in chip self-destruction or at least system failure with the requirement to power down. It is controlled by process innovations and well-understood circuit techniques.

Source of the latch up effect may be explained by examining the process cross-section of a CMOS inverter, shown in fig. 5.17(a), on which is overlaid an equivalent circuit. The schematic shows, in addition to the expected NMOS and MOS transistors, a circuit composed of an npn-transistor, a pnp-transistor, and two resistors connected between the power and ground rails [fig. 5.17(b)]. Under the right conditions, this parasitic circuit has the V/I characteristic shown in fig. 5.17(c), which shows that above some critical voltage the circuit “snaps” and draws a large current while maintaining a low voltage across the terminals. This is, in effect, a short circuit. The bipolar devices and resistors shown in fig. 5.17(b) are parasitic, that is, an undesired byproduct of generating PMOS and NMOS transistors. Further examination of fig. 5.17(a) shows how these devices are constructed, which shows a cross-sectional view of typical (n-well) CMOS process. The (vertical) pnp-transistor has its emitter formed by the p+ source/drain implant used in the PMOS transistors. Either the drain or source may work as the emitter although the source is the only terminal that can maintain the latch up condition. The base is constructed by the n-well, while the collector is the p-substrate. The emitter of the (lateral) npn-transistor is the n+ source/drain implant, while the base is the p-substrate and well resistance Rwell are because of the resistivity of the semiconductors involved.


Let us consider the circuit shown in fig. 5.17(b). when a current is drawn from the npn-emitter, the emitter voltage becomes negative with respect to the base until the base emitter voltage is approximately 0.7 V. at this point the npn-transistor turns-on and a current conducts in the well resistor because of common emitter current amplification of the npn-transistor. This increases the base emitter voltage of the pnp-transistor, which turns on when the pnp Vbe = -0.7 V. this in turn raises the npn base voltage causing a positive feedback condition, which has the characteristic shown in fig. 5.17(c). At a certain npn-base-emitter voltage, known as the trigger point, the emitter voltage suddenly “snaps back” and enters a stable state called the ON state. This state will persist as long as the voltage cross the two transistors is greater than the holding voltage shown in the figure. As the emitter of the npn is the source/drains of the n-transistor, these terminals are now at roughly 4 volts. Hence, there is about 1 volt across the CMOS inverter, which will most likely cause it to stop operating correctly. Generally, the current drawn is destructive to metal lines supplying the latched up circuitry.

Remedies for the latch up problem includes –

  1. An increase in substrate doping levels with a consequent drop in the value of Rsubstrate.
  2. Reducing Rwell by control of fabrication parameters by insulating a low contact resistance to VSS.
  3. Other more elaborate measures such as the introduction of guard rings.

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