## Consider the same transmission scheme and that data are to be Transmitted at a rate of 10,000 bps. If there is a drift between the clock of Transmitted and receiver of 7 per cent (receiver’s clock is faster than transmitter’s clock). Explain what will happened ?

Ans- Since the transmitter clock and receiver clock are running on different

speed, i.e., drift of 7% is observed. The received data will be in synchronization

at start bit but due to accumulative error will go on increasing at a rate of?%

per bit interval, the 7th bit of the information will be erroneous.

Since we have 10000 bit frame and we need to maintain the sampling

point to within the central 50% of the bit period, the maximum clock rate error

which can be tolerated comes out to be 2.5 parts in 105 or in other words the

transmitter clock must be within 5% of the receiver clock. If each bit is of

100µ sec and as receiver clock is faster by 7%, the receiver samples the

incoming bit every 93 µsec. Thus the error starts from 7th bit of data.

This actually results in two errors –

(i) Last two bit incorrectly received.

(ii) Bit count will now be out of alignment and framing error may

occur/reported.